Digital Electronics-Flips-Flops
Digital Electronics-Flips-Flops
1. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
- 10.24 kHz
- 5 kHz
- 30.24 kHz
- 15 kHz
2. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?
- The logic level at the D input is transferred to Q on NGT of CLK.
- The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
- The Q output is ALWAYS identical to the D input when CLK = PGT.
- The Q output is ALWAYS identical to the D input.
3. Propagation delay time, tPLH, is measured from the ________.
- triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
- triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
- preset input to the LOW-to-HIGH transition of the output
- clear input to the HIGH-to-LOW transition of the output
4. How is a J-K flip-flop made to toggle?
- J = 0, K = 0
- J = 1, K = 0
- J = 0, K = 1
- J = 1, K = 1
8. The timing network that sets the output frequency of a 555 astable circuit contains ________.
- three external resistors are used
- two external resistors and an external capacitor are used
- an external resistor and two external capacitors are used
- no external resistor or capacitor is required
9. What is the difference between the enable input of the 7475 and the clock input of the 7474?
- The 7475 is edge-triggered.
- The 7474 is edge-triggered.
10. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.
- parity error checking
- ones catching
- digital discrimination
- digital filtering