Electronic Devices and Circuit Theory-Field-Effect Transistors Questions and Answers

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Q11
A dual-gated MOSFET is
  • A a depletion MOSFET.
  • B an enhancement MOSFET.
  • C a VMOSFET.
  • D either a depletion or an enhancement MOSFET.
Answer: Option D
Q12
What three areas are the drain characteristics of a JFET (VGS = 0) divided into?
  • A ohmic, constant-current, breakdown
  • B pinch-off, constant-current, avalanche
  • C ohmic, constant-voltage, breakdown
Answer: Option A
Q13
In a self-biased JFET circuit, if VD = VDD then ID = ________.
  • A 0
  • B cannot be determined from information above
Answer: Option A
Q14
The resistance of a JFET biased in the ohmic region is controlled by
  • A VD.
  • B VGS.
  • C VS.
  • D VDS.
Answer: Option B
Q15
The resistance of a JFET biased in the ohmic region is controlled by
  • A VD.
  • B VGS.
  • C VS.
  • D VDS.
Answer: Option B
Q16
High input resistance for a JFET is due to
  • A a metal oxide layer.
  • B a large input resistor to the device.
  • C an intrinsic layer.
  • D the gate-source junction being reverse-biased.
Answer: Option D
Q17
For a JFET, the change in drain current for a given change in gate-to-source voltage, with the drain-to-source voltage constant, is
  • A breakdown.
  • B reverse transconductance.
  • C forward transconductance.
  • D self-biasing.
Answer: Option C
Q18
A JFET data sheet specifies VGS(off) = –6 V and IDSS = 8 mA. Find the value of ID when VGS = –3 V.
  • A 2 mA
  • B 4 mA
  • C 8 mA
  • D none of the above
Answer: Option A
Q19
A JFET data sheet specifies VGS(off) = –10 V and IDSS = 8 mA. Find the value of ID when VGS = –3 V.
  • A 2 mA
  • B 1.4 mA
  • C 4.8 mA
  • D 3.92 mA
Answer: Option D
Q20
If VD is less than expected (normal) for a self-biased JFET circuit, then it could be caused by a(n)
  • A open RG.
  • B open gate lead.
  • C FET internally open at gate.
  • D all of the above
Answer: Option D

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