Digital Arithmetic Operations and Circuits Questions and Answers

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Q31
Convert each of the signed decimal numbers to an 8-bit signed binary number (two's-complement). +7        –3        –12
  • A 0000 0111 1111 1101 1111 0100
  • B 1000 0111 0111 1101 0111 0100
  • C 0000 0111 0000 0011 0000 1100
  • D 0000 0111 1000 0011 1000 1100
Answer: Option A
Q32
What is one disadvantage of the ripple-carry adder?
  • A The interconnections are more complex.
  • B More stages are required to a full adder.
  • C It is slow due to propagation time.
  • D All of the above.
Answer: Option C
Q33
Solve this binary problem: 01000110 ÷ 00001010 =
  • A 0111
  • B 10011
  • C 1001
  • D 0011
Answer: Option A
Q34
Convert the decimal numbers 275 and 965 to binary-coded decimal (BCD) and add. Select the BCD code groups that reflect the final answer.
  • A 1101 1110 1010
  • B 1110 1010 1110
  • C 0001 0010 0100 0000
  • D 0010 0011 0100 0000
Answer: Option C
Q35
When multiplying 13 × 11 in binary, what is the third partial product?
  • A 1011
  • B 00000000
  • C 100000
  • D 100001
Answer: Option B
Q36
How many BCD adders would be required to add the numbers 97310 + 3910?
  • A 3
  • B 4
  • C 5
  • D 6
Answer: Option A
Q37
The selector inputs to an arithmetic/logic unit (ALU) determine the:
  • A selection of the IC
  • B arithmetic or logic function
  • C data word selection
  • D clock frequency to be used
Answer: Option B
Q38
An 8-bit register may provide storage for two's-complement codes within which decimal range?
  • A +128 to –128
  • B –128 to +127
  • C +128 to –127
  • D +127 to –127
Answer: Option B
Q39
A full-adder adds ________.
  • A two single bits and one carry bit
  • B two 2-bit binary numbers
  • C two 4-bit binary numbers
  • D two 2-bit numbers and one carry bit
Answer: Option A
Q40
The carry propagation delay in 4-bit full-adder circuits:
  • A is cumulative for each stage and limits the speed at which arithmetic operations are performed
  • B is normally not a consideration because the delays are usually in the nanosecond range
  • C decreases in direct ratio to the total number of full-adder stages
  • D increases in direct ratio to the total number of full-adder stages, but is not a factor in limiting the speed of arithmetic operations
Answer: Option A

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