Digital Arithmetic Operations and Circuits Questions and Answers

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Q41
An input to the mode pin of an arithmetic/logic unit (ALU) determines if the function will be:
  • A one's-complemented
  • B arithmetic or logic
  • C positive or negative
  • D with or without carry
Answer: Option B
Q42
Could the sum output of a full-adder be used as a two-bit parity generator?
  • A TRUE
  • B FALSE
Answer: Option A
Q43
In VHDL, what is a GENERATE statement?
  • A The start statement of a program
  • B Not used in VHDL or ADHL
  • C A way to get the computer to generate a program from a circuit diagram
  • D A way to tell the compiler to replicate several components
Answer: Option D
Q44
Binary subtraction of a decimal 15 from 43 will utilize which two's complement?
  • A 101011
  • B 110000
  • C 011100
  • D 110001
Answer: Option D
Q45
Which of the following is the primary advantage of using binary-coded decimal (BCD) instead of straight binary coding?
  • A Fewer bits are required to represent a decimal number with the BCD code.
  • B BCD codes are easily converted from decimal.
  • C the relative ease of converting to and from decimal
  • D BCD codes are easily converted to straight binary codes.
Answer: Option C
Q46
How many inputs must a full-adder have?
  • A 2
  • B 3
  • C 4
  • D 5
Answer: Option B
Q47
The carry propagation delay in full-adder circuits:
  • A is normally not a consideration because the delays are usually in the nanosecond range.
  • B decreases in a direct ratio to the total number of FA stages.
  • C is cumulative for each stage and limits the speed at which arithmetic operations are performed.
  • D increases in a direct ratio to the total number of FA stages but is not a factor in limiting the speed of arithmetic operations.
Answer: Option C
Q48
What is the difference between a full-adder and a half-adder?
  • A Half-adder has a carry-in.
  • B Full-adder has a carry-in.
  • C Half-adder does not have a carry-out.
  • D Full-adder does not have a carry-out.
Answer: Option B
Q49
The summing outputs of a half- or full-adder are designated by which Greek symbol?
  • A omega
  • B theta
  • C lambda
  • D sigma
Answer: Option D
Q50
The BCD addition of 910 and 710 will give initial code groups of 1001 + 0111. Addition of these groups generates a carry to the next higher position. The correct solution to this problem would be to:
  • A ignore the lowest order code group because 0000 is a valid code group and prefix the carry with three zeros
  • B add 0110 to both code groups to validate the carry from the lowest order code group
  • C disregard the carry and add 0110 to the lowest order code group
  • D add 0110 to the lowest order code group because a carry was generated and then prefix the carry with three zeros
Answer: Option D

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