Flips-Flops Questions and Answers

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Q1
Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
  • A 10.24 kHz
  • B 5 kHz
  • C 30.24 kHz
  • D 15 kHz
Answer: Option B
Q2
Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?
  • A The logic level at the D input is transferred to Q on NGT of CLK.
  • B The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
  • C The Q output is ALWAYS identical to the D input when CLK = PGT.
  • D The Q output is ALWAYS identical to the D input.
Answer: Option A
Q3
Propagation delay time, tPLH, is measured from the ________.
  • A triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
  • B triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
  • C preset input to the LOW-to-HIGH transition of the output
  • D clear input to the HIGH-to-LOW transition of the output
Answer: Option A
Q4
How is a J-K flip-flop made to toggle?
  • A J = 0, K = 0
  • B J = 1, K = 0
  • C J = 0, K = 1
  • D J = 1, K = 1
Answer: Option D
Q5
How many flip-flops are in the 7475 IC?
  • A 1
  • B 2
  • C 4
  • D 8
Answer: Option C
Q6
How many flip-flops are required to produce a divide-by-128 device?
  • A 1
  • B 4
  • C 6
  • D 7
Answer: Option D
Q7
Which is not an Altera primitive port identifier?
  • A clk
  • B ena
  • C clr
  • D prn
Answer: Option C
Q8
The timing network that sets the output frequency of a 555 astable circuit contains ________.
  • A three external resistors are used
  • B two external resistors and an external capacitor are used
  • C an external resistor and two external capacitors are used
  • D no external resistor or capacitor is required
Answer: Option B
Q9
What is the difference between the enable input of the 7475 and the clock input of the 7474?
  • A The 7475 is edge-triggered.
  • B The 7474 is edge-triggered.
Answer: Option B
Q10
The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.
  • A parity error checking
  • B ones catching
  • C digital discrimination
  • D digital filtering
Answer: Option B

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