Flips-Flops Questions and Answers

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Q31
A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
  • A CLK = NGT, D = 0
  • B CLK = PGT, D = 0
  • C CLOCK NGT, D = 1
  • D CLOCK PGT, D = 1
Answer: Option D
Q32
In a 555 timer, three 5 k resistors provide a trigger level of ________.
  • A 1/4 VCC and a threshold level 1/2 VCC
  • B 1/3 VCC and a threshold level 3/4 VCC
  • C 1/3 VCC and a threshold level 2/3 VCC
  • D 1/4 VCC and a threshold level 2/3 VCC
Answer: Option C
Q33
Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?
  • A active-HIGH
  • B active-LOW
Answer: Option A
Q34
The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the:
  • A edge-detection circuit.
  • B NOR latch.
  • C NAND latch.
  • D pulse-steering circuit.
Answer: Option A
Q35
With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?
  • A 16
  • B 8
  • C 4
  • D 2
Answer: Option B
Q36
What is the significance of the J and K terminals on the J-K flip-flop?
  • A There is no known significance in their designations.
  • B The J represents "jump," which is how the Q output reacts whenever the clock goes high and the J input is also HIGH.
  • C The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit.
  • D All of the other letters of the alphabet are already in use.
Answer: Option C
Q37
Why are the S and R inputs of a gated flip-flop said to be synchronous?
  • A They must occur with the gate.
  • B They occur independent of the gate.
Answer: Option A
Q38
Gated S-R flip-flops are called asynchronous because the output responds immediately to input changes.
  • A TRUE
  • B FALSE
Answer: Option B
Q39
Which of the following is not generally associated with flip-flops?
  • A Hold time
  • B Propagation delay time
  • C Interval time
  • D Set up time
Answer: Option C
Q40
Edge-triggered flip-flops must have:
  • A very fast response times
  • B at least two inputs to handle rising and falling edges
  • C positive edge-detection circuits
  • D negative edge-detection circuits
Answer: Option C

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