Flips-Flops Questions and Answers

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Q41
What is one disadvantage of an S-R flip-flop?
  • A It has no enable input.
  • B It has an invalid state.
  • C It has no clock input.
  • D It has only a single output.
Answer: Option B
Q42
To completely load and then unload an 8-bit register requires how many clock pulses?
  • A 2
  • B 4
  • C 8
  • D 16
Answer: Option D
Q43
What is one disadvantage of an S-R flip-flop?
  • A It has no enable input.
  • B It has an invalid state.
  • C It has no clock input.
  • D It has only a single output.
Answer: Option B
Q44
Which of the following best describes the action of pulse-triggered FF's?
  • A The clock and the S-R inputs must be pulse shaped.
  • B The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.
  • C A pulse on the clock transfers data from input to output.
  • D The synchronous inputs must be pulsed.
Answer: Option B
Q45
An invalid condition in the operation of an active-HIGH input S-R latch occurs when ________.
  • A HIGHs are applied simultaneously to both inputs S and R
  • B LOWs are applied simultaneously to both inputs S and R
  • C a LOW is applied to the S input while a HIGH is applied to the R input
  • D a HIGH is applied to the S input while a LOW is applied to the R input
Answer: Option A
Q46
On a J-K flip-flop, when is the flip-flop in a hold condition?
  • A J = 0, K = 0
  • B J = 1, K = 0
  • C J = 0, K = 1
  • D J = 1, K = 1
Answer: Option A
Q47
Edge-triggered flip-flops must have:
  • A very fast response times.
  • B at least two inputs to handle rising and falling edges.
  • C a pulse transition detector.
  • D active-LOW inputs and complemented outputs.
Answer: Option C
Q48
As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:
  • A very long.
  • B very short.
  • C at a maximum value to enable the input control signals to stabilize.
  • D of no consequence as long as the levels are within the determinate range of value.
Answer: Option B
Q49
A positive edge-triggered D flip-flop will store a 1 when ________.
  • A the D input is HIGH and the clock transitions from HIGH to LOW
  • B the D input is HIGH and the clock transitions from LOW to HIGH
  • C the D input is HIGH and the clock is LOW
  • D the D input is HIGH and the clock is HIGH
Answer: Option B
Q50
If an input is activated by a signal transition, it is ________.
  • A edge-triggered
  • B toggle triggered
  • C clock triggered
  • D noise triggered
Answer: Option A

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