Flips-Flops Questions and Answers

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Q21
A J-K flip-flop is in a "no change" condition when ________.
  • A J = 1, K = 1
  • B J = 1, K = 0
  • C J = 0, K = 1
  • D J = 0, K = 0
Answer: Option D
Q22
A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:
  • A clock is LOW
  • B slave is transferring
  • C flip-flop is reset
  • D clock is HIGH
Answer: Option D
Q23
Which of the following describes the operation of a positive edge-triggered D flip-flop?
  • A If both inputs are HIGH, the output will toggle.
  • B The output will follow the input on the leading edge of the clock.
  • C When both inputs are LOW, an invalid state exists
  • D The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
Answer: Option B
Q24
What does the triangle on the clock input of a J-K flip-flop mean?
  • A level enabled
  • B edge-triggered
Answer: Option B
Q25
A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.
  • A constantly LOW
  • B constantly HIGH
  • C a 20 kHz square wave
  • D a 10 kHz square wave
Answer: Option D
Q26
The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________.
  • A opposite, active clock edge
  • B inverted, positive clock edge
  • C quiescent, negative clock edge
  • D reset, synchronous clock edge
Answer: Option A
Q27
On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.
  • A the clock pulse is LOW
  • B the clock pulse is HIGH
  • C the clock pulse transitions from LOW to HIGH
  • D the clock pulse transitions from HIGH to LOW
Answer: Option C
Q28
What is the hold condition of a flip-flop?
  • A both S and R inputs activated
  • B no active S or R input
  • C only S is active
  • D only R is active
Answer: Option B
Q29
If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.
  • A SET
  • B RESET
  • C clear
  • D invalid
Answer: Option B
Q30
In VHDL, how many inputs will a primitive JK flip-flop have?
  • A 2
  • B 3
  • C 4
  • D 5
Answer: Option D

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