Flips-Flops Questions and Answers
Practice ModeShowing 10 of 64 questions
Q51
A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What causes the glitches, and how might the problem be corrected?
Answer: Option D
Q52
Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock input.
Answer: Option B
Q53
Which is not a real advantage of HDL?
Answer: Option C
Q54
Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________.
Answer: Option A
Q55
Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
Answer: Option A
Q56
In VHDL, how is each instance of a component addressed?
Answer: Option A
Q57
The output of a gated S-R flip-flop changes only if the:
Answer: Option B
Q58
In VHDL, in which declaration section is a COMPONENT declared?
Answer: Option A
Q59
If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?
Answer: Option B
Q60
A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?
Answer: Option B