Digital Electronics-Boolean Algebra and Logic Simplification

Digital Electronics-Boolean Algebra and Logic Simplification
11. Use Boolean algebra to find the most simplified SOP expression for F = ABD + CD + ACD + ABC + ABCD.
  • F = ABD + ABC + CD
  • F = CD + AD
  • F = BC + AB
  • F = AC + AD
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12. Occasionally, a particular logic expression will be of no consequence in the operation of a circuit, such as a BCD-to-decimal converter. These result in ________terms in the K-map and can be treated as either ________ or ________, in order to ________ the resulting term.
  • don't care, 1s, 0s, simplify
  • spurious, ANDs, ORs, eliminate
  • duplicate, 1s, 0s, verify
  • spurious, 1s, 0s, simplify
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13. The NAND or NOR gates are referred to as "universal" gates because either:
  • can be found in almost all digital circuits
  • can be used to build all the other types of gates
  • are used in all countries of the world
  • were the first gates to be integrated
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14. The truth table for the SOP expression has how many input combinations?
  • 1
  • 2
  • 4
  • 8
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15. Converting the Boolean expression LM + M(NO + PQ) to SOP form, we get ________.
  • LM + MNOPQ
  • L + MNO + MPQ
  • LM + M + NO + MPQ
  • LM + MNO + MPQ
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16. A Karnaugh map is a systematic way of reducing which type of expression?
  • product-of-sums
  • exclusive NOR
  • sum-of-products
  • those with overbars
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17. Which statement below best describes a Karnaugh map?
  • A Karnaugh map can be used to replace Boolean rules.
  • The Karnaugh map eliminates the need for using NAND and NOR gates.
  • Variable complements can be eliminated by using Karnaugh maps.
  • Karnaugh maps provide a cookbook approach to simplifying Boolean
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18. Which of the examples below expresses the distributive law of Boolean algebra?
  • (A + B) + C = A + (B + C)
  • A(B + C) = AB + AC
  • A + (B + C) = AB + AC
  • A(BC) = (AB) + C
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19. Which of the following is an important feature of the sum-of-products (SOP) form of expression?
  • All logic circuits are reduced to nothing more than simple AND and OR gates
  • The delay times are greatly reduced over other forms.
  • No signal must pass through more than two gates, not including inverters.
  • The maximum number of gates that any signal must pass through is reduced by a factor of two.
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20. An OR gate with schematic "bubbles" on its inputs performs the same functions as a(n)________ gate.
  • NOR
  • OR
  • NOT
  • NAND
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