Digital Electronics-Digital System Projects Using HDL

Digital Electronics-Digital System Projects Using HDL
21. Which is not a step in strategic planning for HDL development?
  • There must be a way to test each piece.
  • Each block must fit together to make up the whole system.
  • The names of each input and output must be known.
  • The exact operation of each block must be thoroughly defined and understood.
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22. In the frequency counter, when is the new count stored in the display register?
  • After disabling the counter
  • When the count buffer is full
  • After the sample interval is set
  • When the timing and control block has put it there
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23. What are two ways to remember the current state of a counter in VHDL?
  • With FUNCTIONS and PROCESS
  • With counters and timers
  • With SIGNAL and VARIABLE
  • With bit types
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24. In the digital clock project, what type of counter is used to count to 59 seconds?
  • MOD-60
  • MOD-6
  • BCD
  • BCD followed by a MOD-6
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25. In the keypad application, when all columns are HIGH, the ring counter is enabled and counting, and dav is LOW, what is the status of the d outputs?
  • On
  • Off
  • Hi-Z
  • 1011
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26. In the frequency counter, what is the function of the Schmitt trigger circuit?
  • To reduce input noise
  • To condition the input signal
  • To convert non-square waveforms
  • To provide a usable signal to the display unit
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27. List three basic blocks in the digital clock project.
  • MOD-60, MOD-12 counters
  • MOD-5, MOD-10, MOD-12 counters
  • MOD-60, MOD-10 counters
  • MOD-6, MOD-12, and MOD-10 counters
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28. When designing an HDL digital system, which is the worst mistake one can make?
  • Concluding that a fundamental block works perfectly
  • Failing to provide proper documentation
  • Adding blocks of code prior to testing them
  • Overlooking a possible VARIABLE
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29. In the keypad application, just after the 4 ms mark the simulation imitates the release of the key by changing the column value back to F hex, which causes the d output to go into its Hi-Z state. On the next rising clock edge, what happens to dav?
  • It goes HIGH.
  • It goes LOW.
  • It goes to Hi-Z.
  • It goes to 1111H.
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30. For the frequency counter, which is not a control signal from the control and timing block?
  • Clear
  • Enable
  • Reset
  • Store
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