Digital Electronics-Flips-Flops
Digital Electronics-Flips-Flops
51. A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What causes the glitches, and how might the problem be corrected?
- The PRESET and CLEAR terminals may have been left floating; they should be properly terminated if not being used.
- The problem is caused by a race condition between the J and K inputs; an inverter should be inserted in one of the terminals to correct the problem.
- A race condition exists between the Q and Q outputs to the AND gate; the AND gate should be replaced with a NAND gate.
- A race condition exists between the clock and the outputs of the flip-flop feeding the AND gate; replace the flip-flop with a negative edge-triggered J-K Flip-Flop. Answer & Explanation
52. Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock input.
- TRUE
- FALSE
53. Which is not a real advantage of HDL?
- Using higher levels of abstraction
- Tailoring components to exactly fit the needs of the project
- The use of graphical tools
- Using higher levels of abstraction and tailoring components to exactly fit the needs of the project
54. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________.
- 00
- 11
- 01
- 10
55. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
- cross coupling
- gate impedance
- low input voltages
- asynchronous operation
56. In VHDL, how is each instance of a component addressed?
- A name followed by a colon and the name of the library primitive
- A name followed by a semicolon and the component type
- A name followed by the library being used
- A name followed by the component library number
57. The output of a gated S-R flip-flop changes only if the:
- flip-flop is set
- control input data has changed
- flip-flop is reset
- input data has no change
58. In VHDL, in which declaration section is a COMPONENT declared?
- Architecture
- Library
- Entity
- Port map
59. If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?
- An invalid state will exist.
- No change will occur in the output.
- The output will toggle.
- The output will reset.
60. A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?
- The power supply is probably noisy.
- The switch contacts are bouncing.
- The socket contacts on the register IC are corroded.
- The register IC is intermittent and failure is imminent.