Digital Electronics-Digital Arithmetic Operations and Circuits

Digital Electronics-Digital Arithmetic Operations and Circuits
41. An input to the mode pin of an arithmetic/logic unit (ALU) determines if the function will be:
  • one's-complemented
  • arithmetic or logic
  • positive or negative
  • with or without carry
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42. Could the sum output of a full-adder be used as a two-bit parity generator?
  • TRUE
  • FALSE
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43. In VHDL, what is a GENERATE statement?
  • The start statement of a program
  • Not used in VHDL or ADHL
  • A way to get the computer to generate a program from a circuit diagram
  • A way to tell the compiler to replicate several components
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44. Binary subtraction of a decimal 15 from 43 will utilize which two's complement?
  • 101011
  • 110000
  • 011100
  • 110001
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45. Which of the following is the primary advantage of using binary-coded decimal (BCD) instead of straight binary coding?
  • Fewer bits are required to represent a decimal number with the BCD code.
  • BCD codes are easily converted from decimal.
  • the relative ease of converting to and from decimal
  • BCD codes are easily converted to straight binary codes.
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46. How many inputs must a full-adder have?
  • 2
  • 3
  • 4
  • 5
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47. The carry propagation delay in full-adder circuits:
  • is normally not a consideration because the delays are usually in the nanosecond range.
  • decreases in a direct ratio to the total number of FA stages.
  • is cumulative for each stage and limits the speed at which arithmetic operations are performed.
  • increases in a direct ratio to the total number of FA stages but is not a factor in limiting the speed of arithmetic operations.
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48. What is the difference between a full-adder and a half-adder?
  • Half-adder has a carry-in.
  • Full-adder has a carry-in.
  • Half-adder does not have a carry-out.
  • Full-adder does not have a carry-out.
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49. The summing outputs of a half- or full-adder are designated by which Greek symbol?
  • omega
  • theta
  • lambda
  • sigma
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50. The BCD addition of 910 and 710 will give initial code groups of 1001 + 0111. Addition of these groups generates a carry to the next higher position. The correct solution to this problem would be to:
  • ignore the lowest order code group because 0000 is a valid code group and prefix the carry with three zeros
  • add 0110 to both code groups to validate the carry from the lowest order code group
  • disregard the carry and add 0110 to the lowest order code group
  • add 0110 to the lowest order code group because a carry was generated and then prefix the carry with three zeros
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