Digital Electronics-Shift Registers

Digital Electronics-Shift Registers
51. When the output of a tristate shift register is disabled, the output level is placed in a:
  • float state
  • LOW state
  • high-impedance state
  • float or high-impedance state
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52. One of the stages in a register consists of a latch.
  • TRUE
  • FALSE
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53. There are several ways to construct a stepper motor to achieve digitally controlled stepping action. One possibility is to construct four stator coils set up as four pole pairs, each 45° apart and using three ferromagnetic pairs spaced 60° apart.
  • TRUE
  • FALSE
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54. A parallel load operation is asynchronous, so it is not dependent on the clock.
  • TRUE
  • FALSE
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55. A ferromagnetic material is one that forms a resistance to magnetic fields.
  • TRUE
  • FALSE
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56. A counter has a specified sequence of states, but a shift register does not.
  • TRUE
  • FALSE
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57. In a 74164 8-bit shift register, in order for the parallel data output to be synchronously loaded on the negative clock edge, the parallel enable input is LOW.
  • TRUE
  • FALSE
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58. Practically every possible load, shift, and conversion operation is available in a shift register IC.
  • TRUE
  • FALSE
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59. Using separate serial inputs for shifting left or shifting right is a major difference between the 74194 and other shift registers.
  • TRUE
  • FALSE
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60. Parallel load means to load all flip-flops at the same time.
  • TRUE
  • FALSE
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